19 search results - page 4 / 4 » Formal Verification of a DSP Chip Using an Iterative Approac... |
POPL
2009
ACM
14 years 8 months ago
2009
ACM
We present a proof calculus and method for the static verification of assertions and procedure specifications in shared-memory concurrent programs. The key idea in our approach is...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...