294 search results - page 15 / 59 » Formal Verification of the Implementability of Timing Requir... |
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Reusable software components need well-defined interfaces, rigorously and completely documented features, and a design amenable both to reuse and to formal verification; all these...
ACSD
2001
IEEE
13 years 11 months ago
2001
IEEE
One of the corner stones of formal methods is the notion traction enables analysis. By the construction of act model we can trade implementation detail for analytical power. The i...
CJ
2004
13 years 7 months ago
2004
Digital signatures have been proposed by several researchers as a way of preventing execution of malicious code. In this paper we propose a general architecture for performing the...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
EUROMICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...