294 search results - page 31 / 59 » Formal Verification of the Implementability of Timing Requir... |
ANSOFT
2002
13 years 8 months ago
2002
Abstract. The real-time process algebra (RTPA) is a set of new mathematical notations for formally describing system architectures, and static and dynamic behaviors. It is recogniz...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
DBSEC
2007
13 years 10 months ago
2007
Abstract. Modern information systems require temporal and privilegeconsuming usage of digital objects. To meet these requirements, we present a new access control model–Times-bas...
FORMATS
2007
Springer
14 years 2 months ago
2007
Springer
Dierence Bound Matrices (DBMs) are the most commonly used data structure for model checking timed automata. Since long they are being used in successful tools like Kronos or UPPAA...
DAC
2007
ACM
14 years 13 days ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...