294 search results - page 36 / 59 » Formal Verification of the Implementability of Timing Requir... |
LPAR
2010
Springer
13 years 6 months ago
2010
Springer
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
BIRTHDAY
2012
Springer
12 years 4 months ago
2012
Springer
We propose a new countermeasure to protect block ciphers implemented in leaking devices, at the intersection between One-Time Programs and Boolean masking schemes. First, we show t...
IJCAI
1993
13 years 9 months ago
1993
The problem of representing and reasoning about two notions of time that are relevant in the context of knowledge bases is addressed. These are called historical time and belief t...
FASE
2000
Springer
14 years 2 days ago
2000
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and f...