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» Formal Verification of the Ricart-Agrawala Algorithm
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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ESOP
2010
Springer
14 years 4 months ago
Formal Verification of Coalescing Graph-Coloring Register Allocation
Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less...
Andrew W. Appel, Benoît Robillard, Sandrine ...
ASIAN
2006
Springer
118views Algorithms» more  ASIAN 2006»
13 years 11 months ago
An Approach to Formal Verification of Arithmetic Functions in Assembly
Abstract. It is customary to write performance-critical parts of arithmetic functions in assembly: this enables finely-tuned algorithms that use specialized processor instructions....
Reynald Affeldt, Nicolas Marti
CHARME
1997
Springer
105views Hardware» more  CHARME 1997»
13 years 11 months ago
Simulation-based verification of network protocols performance
Formal verification techniques need to deal with the complexity of the systems rified. Most often, this problem is solved by taking an abstract model of the system and aiming at a...
Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Pa...
PTS
2010
175views Hardware» more  PTS 2010»
13 years 5 months ago
Test Data Generation for Programs with Quantified First-Order Logic Specifications
We present a novel algorithm for test data generation that is based on techniques used in formal software verification. Prominent examples of such formal techniques are symbolic ex...
Christoph Gladisch