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» Formal analysis of hardware requirements
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VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 11 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
RV
2009
Springer
101views Hardware» more  RV 2009»
14 years 5 months ago
DMaC: Distributed Monitoring and Checking
Abstract. We consider monitoring and checking formally specified properties in a network. We are addressing the problem of deploying the checkers on different network nodes that ...
Wenchao Zhou, Oleg Sokolsky, Boon Thau Loo, Insup ...
TAP
2008
Springer
102views Hardware» more  TAP 2008»
13 years 10 months ago
A Logic-Based Approach to Combinatorial Testing with Constraints
Abstract. Usage of combinatorial testing is wide spreading as an effective technique to reveal unintended feature interaction inside a given system. To this aim, test cases are con...
Andrea Calvagna, Angelo Gargantini
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 4 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
SIGSOFT
2010
ACM
13 years 8 months ago
Differential static analysis: opportunities, applications, and challenges
It is widely believed that program analysis can be more closely targeted to the needs of programmers if the program is accompanied by further redundant documentation. This may inc...
Shuvendu K. Lahiri, Kapil Vaswani, C. A. R. Hoare