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» Formal analysis of hardware requirements
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CODES
2007
IEEE
14 years 3 months ago
Locality optimization in wireless applications
There is a strong need now for compilers of embedded systems to find effective ways of optimizing series of loop-nests, wherein majority of the memory references occur in the fo...
Javed Absar, Min Li, Praveen Raghavan, Andy Lambre...
CAV
2007
Springer
116views Hardware» more  CAV 2007»
14 years 3 months ago
A Decision Procedure for Bit-Vectors and Arrays
Abstract. STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encoun...
Vijay Ganesh, David L. Dill
CAV
2004
Springer
123views Hardware» more  CAV 2004»
14 years 2 months ago
SAL 2
SAL 2 augments the specification language and explicit-state model checker of SAL 1 with high-performance symbolic and bounded model checkers, and with novel infinite bounded and...
Leonardo Mendonça de Moura, Sam Owre, Haral...
CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
14 years 2 months ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
HPCA
2000
IEEE
14 years 1 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...