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EUROCRYPT
2007
Springer
14 years 3 months ago
Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit
Significant progress in the design of special purpose hardware for supporting the Number Field Sieve (NFS) has been made. From a practical cryptanalytic point of view, however, no...
Willi Geiselmann, Rainer Steinwandt
SMI
2006
IEEE
209views Image Analysis» more  SMI 2006»
14 years 3 months ago
Hardware Rendering of 3D Geometry with Elevation Maps
We present a generic framework for realtime rendering of 3D surfaces. We use the common elevation map primitive, by which a given surface is decomposed into a set of patches. Each...
Tilo Ochotta, Stefan Hiller
CTRSA
2003
Springer
96views Cryptology» more  CTRSA 2003»
14 years 2 months ago
Hardware Performance Characterization of Block Cipher Structures
In this paper, we present a general framework for evaluating the performance characteristics of block cipher structures composed of S-boxes and Maximum Distance Separable (MDS) ma...
Lu Xiao, Howard M. Heys
PAIRING
2010
Springer
153views Cryptology» more  PAIRING 2010»
13 years 7 months ago
Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such cu...
Nicolas Estibals
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 3 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin