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» Formal specification: a roadmap
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FDL
2007
IEEE
14 years 4 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
WER
2007
Springer
14 years 3 months ago
Test-case Driven versus Checklist-based Inspections of Software Requirements - An Experimental Evaluation
Software inspections have proved to be an effective means to find faults in different software artifacts, and the application of software inspections on requirements specification...
Nina Dzamashvili-Fogelström, Tony Gorschek
SEFM
2005
IEEE
14 years 3 months ago
Experimental Evaluation of FSM-Based Testing Methods
The development of test cases is an important issue for testing software, communication protocols and other reactive systems. A number of methods are known for the development of ...
Rita Dorofeeva, Nina Yevtushenko, Khaled El-Fakih,...
APSEC
2003
IEEE
14 years 2 months ago
Selecting Components: a Process for Context-Driven Evaluation
This paper describes a process for selecting and evaluating candidates for component based software engineering. The process is aimed at developers sourcing components from third ...
Valerie Maxville, Chiou Peng Lam, Jocelyn Armarego
IFIP
2009
Springer
14 years 2 months ago
Supporting Cross-Organizational Process Control
E-contracts express the rights and obligations of parties through a formal, digital representation of the contract provisions. In process intensive relationships, e-contracts conta...
Samuil Angelov, Jochem Vonk, Krishnamurthy Vidyasa...