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» Formal specification: a roadmap
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ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
15 years 8 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
FDL
2004
IEEE
15 years 8 months ago
The Formal Simulation Semantics of SystemVerilog
We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the s...
Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. M&uu...
CLA
2004
15 years 5 months ago
Ontology Design with Formal Concept Analysis
Ontologies, often defined as an explicit specification of conceptualization, are necessary for knowledge representation and knowledge exchange. Usually this means that ontology des...
Marek Obitko, Václav Snásel, Jan Smi...
FORTE
1998
15 years 5 months ago
Hardware - Software Co-design of embedded telecommunication systems using multiple formalisms for application development
: In this paper a co-design methodology based on multiformalism modelling is presented. It defines a platform that integrates different notations and, the necessary mechanisms to h...
Nikos S. Voros, S. K. Tsasakou, C. Valderrama, S. ...
FLAIRS
2000
15 years 5 months ago
The Use of Formal Methods for Trusted Digital Signature Devices
This paper presents a formal security policy model for SmartCards with digital signature application. This kind of model is necessary for each evaluation according to Information ...
Bruno Langenstein, Roland Vogt, Markus Ullmann