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» Formal verification of analog designs using MetiTarski
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ICCD
2000
IEEE
119views Hardware» more  ICCD 2000»
13 years 11 months ago
Source-Level Transformations for Improved Formal Verification
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
Brian D. Winters, Alan J. Hu
JCP
2008
116views more  JCP 2008»
13 years 7 months ago
Formal Verification and Visualization of Security Policies
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
Luay A. Wahsheh, Daniel Conte de Leon, Jim Alves-F...
FORMATS
2007
Springer
13 years 11 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
AMCS
2011
341views Mathematics» more  AMCS 2011»
13 years 2 months ago
FSP and FLTL framework for specification and verification of middle-agents
Agents are a useful abstraction frequently employed as a basic building block in modeling service, information and resource sharing in global environments. The connecting of reques...
Amelia Badica, Costin Badica
CAV
1994
Springer
111views Hardware» more  CAV 1994»
13 years 11 months ago
Automatic Verification of Timed Circuits
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
Tomas Rokicki, Chris J. Myers