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» Formal verification of analog designs using MetiTarski
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DAC
2007
ACM
13 years 11 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
ARTS
1997
Springer
13 years 11 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
CAV
2009
Springer
206views Hardware» more  CAV 2009»
14 years 8 months ago
D-Finder: A Tool for Compositional Deadlock Detection and Verification
D-Finder tool implements a compositional method for the verification of component-based systems described in BIP language encompassing multi-party interaction. For deadlock detecti...
Saddek Bensalem, Marius Bozga, Thanh-Hung Nguyen, ...
DAC
2006
ACM
14 years 8 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
FM
1999
Springer
97views Formal Methods» more  FM 1999»
13 years 11 months ago
Sensors and Actuators in TCOZ
Timed Communicating Object Z (TCOZ) combines Object-Z's strengths in modeling complex data and algorithms with Timed CSP's strengths in modeling real-time concurrency. TC...
Brendan P. Mahony, Jin Song Dong