299 search results - page 6 / 60 » Formal verification of analog designs using MetiTarski |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
FMCAD
2006
Springer
13 years 11 months ago
2006
Springer
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
ISQED
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...