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» Formally Specifying and Verifying Real-Time Systems
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HVC
2007
Springer
153views Hardware» more  HVC 2007»
13 years 11 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul
CL
2008
Springer
13 years 7 months ago
Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
Pao-Ann Hsiung, Shang-Wei Lin
ICFEM
2003
Springer
14 years 22 days ago
Formal Proof of a Polychronous Protocol for Loosely Time-Triggered Architectures
The verification of safety critical systems has become an area of increasing importance in computer science. The notion of reactive system has emerged to concentrate on problems r...
Mickaël Kerboeuf, David Nowak, Jean-Pierre Ta...
COMCOM
1998
117views more  COMCOM 1998»
13 years 7 months ago
Specification, validation, and verification of time-critical systems
In this paper, we propose a new formalism, named the Timed Communicating Finite State Machine (Timed CFSM), for specifying and verifying time-critical systems. Timed CFSM preserve...
Shiuh-Pyng Shieh, Jun-Nan Chen
ENTCS
2008
118views more  ENTCS 2008»
13 years 7 months ago
The STSLib Project: Towards a Formal Component Model Based on STS
We present the current state of our STSLib project. This project aims at defining an environment to formally specify and execute software components. One important feature is that...
Fabrício Fernandes, Jean-Claude Royer