On the Architecture of System Verification Environments

Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying tool chain. The Verisoft project deals with the formal pervasive verification of computer systems. Making use of appropriate formal specification and proof tools, this task requires (i) specifying the layers and languages used in the implementation, (ii) specifying and verifying the algorithms employed by the tool chain (or, alternatively, validating their actual output), and (iii) proving simulation statements between layers, arguing about the programs residing at the different layers. Combining the simulation statements for all layers should allow to transfer correctness results for top-layer programs to their bottom-layer representation; in this manner, a verified stack can be built. Maintaining all formal artifacts, the actual system implementation, and the (verification) tool chain is a challenging task. We...

• Type: Conference
• Year: 2007
• Where: HVC
• Authors: Mark A. Hillebrand, Wolfgang J. Paul
• Keywords: Formal Pervasive Verification, Hardware, HVC 2007, Simulation Statements, Tool Chain