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» Fractal Coherence: Scalably Verifiable Cache Coherence
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ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
12 years 11 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
DSN
2011
IEEE
12 years 7 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
12 years 11 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
KDD
2003
ACM
152views Data Mining» more  KDD 2003»
14 years 7 months ago
Interactive exploration of coherent patterns in time-series gene expression data
Discovering coherent gene expression patterns in time-series gene expression data is an important task in bioinformatics research and biomedical applications. In this paper, we pr...
Daxin Jiang, Jian Pei, Aidong Zhang
WMPI
2004
ACM
14 years 24 days ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar