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» From Design Patterns to Parallel Architectural Skeletons
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RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
HPCA
2008
IEEE
14 years 8 months ago
Fundamental performance constraints in horizontal fusion of in-order cores
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
Pierre Salverda, Craig B. Zilles
HPCA
2004
IEEE
14 years 8 months ago
Perceptron-Based Branch Confidence Estimation
Pipeline gating has been proposed for reducing wasted speculative execution due to branch mispredictions. As processors become deeper or wider, pipeline gating becomes more import...
Haitham Akkary, Srikanth T. Srinivasan, Rajendar K...
CCS
2007
ACM
14 years 1 months ago
SecureBus: towards application-transparent trusted computing with mandatory access control
The increasing number of software-based attacks has attracted substantial efforts to prevent applications from malicious interference. For example, Trusted Computing (TC) technolo...
Xinwen Zhang, Michael J. Covington, Songqing Chen,...
IEEEPACT
2006
IEEE
14 years 1 months ago
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...