53 search results - page 3 / 11 » From Equation to VHDL: Using Rewriting Logic for Automated F... |
JUCS
2006
13 years 7 months ago
2006
Abstract: We present a novel approach to the verification of functional-logic programs. For our verification purposes, equational reasoning is not valid due to the presence of non-...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
ENTCS
2007
13 years 7 months ago
2007
In modern functional logic languages like Curry or Toy, programs are possibly non-confluent and nonterminating rewrite systems, defining possibly non-deterministic non-strict fu...
IICAI
2007
13 years 9 months ago
2007
The paper presents first results of a project that aims at building a model-based tool for functional testing of control software for passenger vehicles. The objective is that this...
AMOST
2007
ACM
13 years 11 months ago
2007
ACM
Model-checkers have recently been suggested for automated software test-case generation. Several works have presented methods that create efficient test-suites using model-checker...