53 search results - page 8 / 11 » From Equation to VHDL: Using Rewriting Logic for Automated F... |
VMCAI
2010
Springer
14 years 4 months ago
2010
Springer
Abstract. Techniques such as verification condition generation, preditraction, and expressive type systems reduce software verification to proving formulas in expressive logics. Pr...
PLDI
2009
ACM
14 years 8 months ago
2009
ACM
High-level languages are growing in popularity. However, decades of C software development have produced large libraries of fast, timetested, meritorious code that are impractical...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to pr...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
KDD
2003
ACM
14 years 7 months ago
2003
ACM
In today's industry, the design of software tests is mostly based on the testers' expertise, while test automation tools are limited to execution of pre-planned tests on...