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ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
14 years 1 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
COLT
2001
Springer
13 years 12 months ago
Tracking a Small Set of Experts by Mixing Past Posteriors
In this paper, we examine on-line learning problems in which the target concept is allowed to change over time. In each trial a master algorithm receives predictions from a large ...
Olivier Bousquet, Manfred K. Warmuth
IISWC
2006
IEEE
14 years 1 months ago
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
Dong Ye, Joydeep Ray, Christophe Harle, David R. K...
CMG
2003
13 years 8 months ago
Virtual Memory Constraints in 32-bit Windows
Many server workloads can exhaust the 32-bit virtual address space in the Windows server operating systems. Machines configured with 2 GB or more of RAM installed are particularly...
Mark B. Friedman
JAR
2006
103views more  JAR 2006»
13 years 7 months ago
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures
We describe an approach to verifying bit-level pipelined machine models using a combination of deductive reasoning and decision procedures. While theorem proving systems such as AC...
Panagiotis Manolios, Sudarshan K. Srinivasan