Background: Graphs and networks are common analysis representations for biological systems. Many traditional graph algorithms such as k-clique, k-coloring, and subgraph matching h...
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
We describe a new procedure for verifying ACL2 properties about finite state machines (FSMs) using satisfiability (SAT) solving. We present an algorithm for converting ACL2 conj...
We propose a novel approach for de ning and querying a super-peer within a schema-based super-peer network organized into a two-level architecture: the low level, called the peer l...
Most current mobile technologies require on-screen operations for interacting with devices’ visual contents. However, as a trade-off for mobility, screens usually provide limite...