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» Functional Validation of Programmable Architectures
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FAC
2008
97views more  FAC 2008»
13 years 8 months ago
A functional formalization of on chip communications
This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Julien Schmaltz, Dominique Borrione
DAC
1999
ACM
14 years 9 months ago
Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks
A number of researchers have proposed using digital marks to provide ownership identification for intellectual property. Many of these techniques share three specific weaknesses: ...
John Lach, William H. Mangione-Smith, Miodrag Potk...
ICPP
1999
IEEE
14 years 1 months ago
Parallel Media Processors for the Billion-Transistor Era
This paper describes the challenges presented by singlechip parallel media processors (PMPs). These machines integrate multiple parallel function units, instruction execution, and...
Jason Fritts, Zhao Wu, Wayne Wolf
ICFP
2008
ACM
14 years 8 months ago
Space profiling for parallel functional programs
This paper presents a semantic space profiler for parallel functional programs. Building on previous work in sequential profiling, our tools help programmers to relate runtime res...
Daniel Spoonhower, Guy E. Blelloch, Robert Harper,...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
14 years 10 days ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham