409 search results - page 46 / 82 » Functional Validation of Programmable Architectures |
SAC
2009
ACM
14 years 3 months ago
2009
ACM
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
ANCS
2005
ACM
14 years 2 months ago
2005
ACM
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
ICCAD
1997
IEEE
14 years 1 months ago
1997
IEEE
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
HIPEAC
2009
Springer
14 years 22 days ago
2009
Springer
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
ERSA
2007
13 years 10 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...