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» Functional debugging of systems-on-chip
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PATMOS
2000
Springer
13 years 11 months ago
Early Power Estimation for System-on-Chip Designs
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reo...
CODES
2009
IEEE
14 years 2 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
ENTCS
2007
120views more  ENTCS 2007»
13 years 7 months ago
A Framework for Interpreting Traces of Functional Logic Computations
This paper is part of a comprehensive approach to debugging for functional logic languages. The basic idea of the whole project is to trace the execution of functional logic progr...
Bernd Braßel
ICCAD
1998
IEEE
76views Hardware» more  ICCAD 1998»
13 years 11 months ago
Functional debugging of systems-on-chip
Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
OOPSLA
2009
Springer
14 years 1 months ago
Debug all your code: portable mixed-environment debugging
Programmers build large-scale systems with multiple languages to reuse legacy code and leverage languages best suited to their problems. For instance, the same program may use Jav...
Byeongcheol Lee, Martin Hirzel, Robert Grimm, Kath...