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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 2 days ago
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
Debasish Das, Kip Killpack, Chandramouli V. Kashya...
TCAD
2008
112views more  TCAD 2008»
13 years 10 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
CORR
2002
Springer
93views Education» more  CORR 2002»
13 years 10 months ago
Logic program specialisation through partial deduction: Control issues
Program specialisation aims at improving the overall performance of programs by performing source to source transformations. A common approach within functional and logic programm...
Michael Leuschel, Maurice Bruynooghe
BIRTHDAY
2010
Springer
13 years 7 months ago
A Logic for PTIME and a Parameterized Halting Problem
In [7] Nash, Remmel, and Vianu have raised the question whether a logic L, already introduced by Gurevich in 1988, captures polynomial time, and they give a reformulation of this ...
Yijia Chen, Jörg Flum
FAC
2010
93views more  FAC 2010»
13 years 7 months ago
Inter-process buffers in separation logic with rely-guarantee
Separation logic allows simple proofs of concurrent algorithms which use blocking mechanisms such as semaphores. It can even deal with non-blocking algorithms. With the addition of...
Richard Bornat, Hasan Amjad