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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 5 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
ICLP
1997
Springer
14 years 24 days ago
Parallel Evaluation Strategies for Functional Logic Languages
We introduce novel, sound, complete, and locally optimal evaluation strategies for functional logic programming languages. Our strategies combine, in a non-trivial way, two landma...
Sergio Antoy, Rachid Echahed, Michael Hanus
ENTCS
2007
114views more  ENTCS 2007»
13 years 8 months ago
Reporting Failures in Functional Logic Programs
Computing with failures is a typical programming technique in functional logic programs. However, there are also situations where a program should not fail (e.g., in a determinist...
Michael Hanus
TCAD
1998
125views more  TCAD 1998»
13 years 8 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
IFL
2004
Springer
14 years 2 months ago
A Virtual Machine for Functional Logic Computations
Abstract. We describe the architecture of a virtual machine for executing functional logic programming languages. A distinguishing feature of our machine is that it preserves the o...
Sergio Antoy, Michael Hanus, Jimeng Liu, Andrew P....