138 search results - page 20 / 28 » Functional test generation for delay faults in combinational... |
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
VTS
2002
IEEE
14 years 18 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
EVOW
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. We motivate and describe an analog evolvable hardware design platform named GRACE (i.e. Generative Robust Analog Circuit Exploration). GRACE combines coarse-grained, topo...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...