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DEBS
2011
ACM
14 years 7 months ago
DejaVu: a complex event processing system for pattern matching over live and historical data streams
This short paper provides an overview of the DejaVu complex event processing (CEP) system, with an emphasis on its novel architecture and query optimization techniques for correla...
Nihal Dindar, Peter M. Fischer, Nesime Tatbul
127
Voted
HPCA
2003
IEEE
16 years 4 months ago
Exploring the VLSI Scalability of Stream Processors
Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area- and energy-efficient th...
Brucek Khailany, William J. Dally, Scott Rixner, U...
138
Voted
ARC
2008
Springer
141views Hardware» more  ARC 2008»
15 years 5 months ago
A Parallel Hardware Architecture for Image Feature Detection
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
Vanderlei Bonato, Eduardo Marques, George A. Const...
154
Voted
CODES
2009
IEEE
15 years 5 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...
125
Voted
IPPS
2006
IEEE
15 years 10 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...