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» Game Engineering for a Multiprocessor Architecture
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DSN
2007
IEEE
14 years 3 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
EMSOFT
2005
Springer
14 years 2 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
CBSE
2006
Springer
14 years 13 days ago
A Process for Resolving Performance Trade-Offs in Component-Based Architectures
Designing architectures requires the balancing of multiple system quality objectives. In this paper, we present techniques that support the exploration of the quality properties of...
Egor Bondarev, Michel R. V. Chaudron, Peter H. N. ...
ARCS
2006
Springer
14 years 14 days ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...
VLSI
2007
Springer
14 years 2 months ago
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
Pranav Vaidya, Jaehwan John Lee