694 search results - page 68 / 139 » Gate Sizing Using a Statistical Delay Model |
128
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ISPD
2004
ACM
15 years 7 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
110
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MASCOTS
2007
15 years 3 months ago
2007
Network performance analysis relies mainly on two models: a workload model and a performance model. This paper proposes to use histograms for characterising the arrival workloads ...
117
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IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
1 Profile Hidden Markov Models (profile HMMs) are used as a popular bioinformatics tool for sensitive database searching, e.g. a set of not annotated protein sequences is compared...
131
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SDL
2003
15 years 3 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
115
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DATE
2009
IEEE
15 years 9 months ago
2009
IEEE
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...