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ITCC
2005
IEEE
14 years 3 months ago
ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives
Hash algorithms are a class of cryptographic primitives used for fulfilling the requirements of integrity and authentication in cryptography. In this paper, we propose and present...
T. S. Ganesh, T. S. B. Sudarshan
WISA
2007
Springer
14 years 3 months ago
Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations
Abstract. The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have be...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
14 years 3 months ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...
IJCAI
1997
13 years 11 months ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
PPSN
2004
Springer
14 years 3 months ago
Evolving Genetic Regulatory Networks for Hardware Fault Tolerance
We present a new approach that is able to produce an increased fault tolerance in bio-inspired electronic circuits. To this end, we designed hardwarefriendly genetic regulatory net...
Arne Koopman, Daniel Roggen