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ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
14 years 5 months ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 4 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
LPNMR
2004
Springer
14 years 4 months ago
Towards Automated Integration of Guess and Check Programs in Answer Set Programming
Abstract. Many NP-complete problems can be encoded in the answer set semantics of logic programs in a very concise way, where the encoding reflects the typical “guess and check...
Thomas Eiter, Axel Polleres
ATAL
2010
Springer
13 years 12 months ago
CTL.STIT: enhancing ATL to express important multi-agent system verification properties
We present the logic CTL.STIT, which is the join of the logic CTL with a multi-agent strategic stit-logic variant. CTL.STIT subsumes ATL, and adds expressivity to it that we claim...
Jan Broersen
ENTCS
2002
90views more  ENTCS 2002»
13 years 10 months ago
A Language for Multi-dimensional Updates
Dynamic Logic Programming (DLP) was introduced to deal with knowledge about changing worlds, by assigning semantics to sequences of generalized logic programs, each of which repres...
João Alexandre Leite, José Jú...