ISMVL 2007 - PDF Preprint Papers

ISMVL 2007 IEEE International Symposium on Multiple-Valued Logic

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ISMVL
2007
IEEE

245views Hardware» more ISMVL 2007»

Fault Tolerant CMOS Logic Using Ternary Gates

14 years 5 months ago

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In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...

Yngvar Berg, Renè Jensen, Johannes Goplen L...

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Id	Views	Title	Status

1	245	Fault Tolerant CMOS Logic Using Ternary Gates	claim
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