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» Generalised Resource Model for Parallel Instruction Scheduli...
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PLDI
1996
ACM
13 years 11 months ago
A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...
Alexandre E. Eichenberger, Edward S. Davidson
ICS
1995
Tsinghua U.
13 years 11 months ago
Optimum Modulo Schedules for Minimum Register Requirements
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
ASPLOS
2008
ACM
13 years 9 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
SODA
2001
ACM
125views Algorithms» more  SODA 2001»
13 years 8 months ago
Parallel processor scheduling with delay constraints
We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose ...
Daniel W. Engels, Jon Feldman, David R. Karger, Ma...