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IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
13 years 28 days ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
VEE
2012
ACM
226views Virtualization» more  VEE 2012»
12 years 5 months ago
Protecting applications against TOCTTOU races by user-space caching of file metadata
Time Of Check To Time Of Use (TOCTTOU) race conditions for file accesses in user-space applications are a common problem in Unix-like systems. The mapping between filename and i...
Mathias Payer, Thomas R. Gross
SDM
2009
SIAM
149views Data Mining» more  SDM 2009»
14 years 7 months ago
Speeding Up Secure Computations via Embedded Caching.
Most existing work on Privacy-Preserving Data Mining (PPDM) focus on enabling conventional data mining algorithms with the ability to run in a secure manner in a multi-party setti...
K. Zhai, W. K. Ng, A. R. Herianto, S. Han
ICS
2007
Tsinghua U.
14 years 4 months ago
Performance driven data cache prefetching in a dynamic software optimization system
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
Jean Christophe Beyler, Philippe Clauss
CAV
1998
Springer
175views Hardware» more  CAV 1998»
14 years 2 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore