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» Generating Tests for Control Portion of SDL Specifications
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BMCBI
2006
169views more  BMCBI 2006»
13 years 7 months ago
Comparative analysis of haplotype association mapping algorithms
Background: Finding the genetic causes of quantitative traits is a complex and difficult task. Classical methods for mapping quantitative trail loci (QTL) in miceuse an F2 cross b...
Phillip McClurg, Mathew T. Pletcher, Tim Wiltshire...
ICCTA
2007
IEEE
13 years 10 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
13 years 10 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
ICTAI
1992
IEEE
13 years 11 months ago
Automated Parameter Tuning in Stereo Vision Under Time Constraints
This paper presents a method for tuning parameters under a fixed time constraint for a general binocular stereo-vision algorithm. A major difficulty in stereo vision, as well as i...
Steven R. Schwartz, Benjamin W. Wah
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 3 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz