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» Generating Unit Tests from Formal Proofs
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GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 6 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
SAC
2008
ACM
13 years 8 months ago
UML-based design test generation
In this paper we investigate and propose a fully automated technique to perform conformance checking of Java implementations against UML class diagrams. In our approach, we reused...
Waldemar Pires, João Brunet, Franklin Ramal...
TASE
2009
IEEE
14 years 3 months ago
Fault-Based Test Case Generation for Component Connectors
The complex interactions appearing in service-oriented computing make coordination a key concern in serviceoriented systems. In this paper, we present a fault-based method to gene...
Bernhard K. Aichernig, Farhad Arbab, Lacramioara A...
FATES
2003
Springer
14 years 1 months ago
Property Oriented Test Case Generation
Abstract. In this paper we propose an approach to automatically produce test cases allowing to check the satis ability of a linear property on a given implementation. Linear proper...
Jean-Claude Fernandez, Laurent Mounier, Cyril Pach...
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
14 years 9 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...