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PLDI
2010
ACM
14 years 3 months ago
A GPGPU compiler for memory optimization and parallelism management
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
CSFW
2002
IEEE
14 years 3 months ago
Security Protocol Design via Authentication Tests
We describe a protocol design process, and illustrate its use by creating ATSPECT, an Authentication Test-based Secure Protocol for Electronic Commerce Transactions. The design pr...
Joshua D. Guttman
IEEEPACT
2002
IEEE
14 years 3 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
HPCC
2009
Springer
14 years 2 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
CRYPTO
2001
Springer
152views Cryptology» more  CRYPTO 2001»
14 years 2 months ago
Secure Distributed Linear Algebra in a Constant Number of Rounds
Consider a network of processors among which elements in a finite field K can be verifiably shared in a constant number of rounds. Assume furthermore constant-round protocols ar...
Ronald Cramer, Ivan Damgård