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» Generating high performance pruned FFT implementations
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ICS
2005
Tsinghua U.
14 years 2 months ago
Think globally, search locally
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
Kamen Yotov, Keshav Pingali, Paul Stodghill
KI
2005
Springer
14 years 2 months ago
Hybrid Planning Using Flexible Strategies
In this paper we present a highly modular planning system architecture. It is based on a proper formal account of hybrid planning, which allows for the formal definition of (flex...
Bernd Schattenberg, Andreas Weigl, Susanne Biundo
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 2 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
FPL
2004
Springer
205views Hardware» more  FPL 2004»
14 years 2 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 2 months ago
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri