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» Generating high performance pruned FFT implementations
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DATE
2007
IEEE
72views Hardware» more  DATE 2007»
14 years 1 months ago
The impact of loop unrolling on controller delay in high level synthesis
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan ...
ACL
1993
13 years 8 months ago
Guiding an HPSG Parser using Semantic and Pragmatic Expectations
1 Efficient natural language generation has been successfully demonstrated using highly compiled knowledge about speech acts and their related social actions. A design and prototyp...
Jim Skon
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
IPPS
2010
IEEE
13 years 5 months ago
pFANGS: Parallel high speed sequence mapping for Next Generation 454-roche Sequencing reads
Millions of DNA sequences (reads) are generated by Next Generation Sequencing machines everyday. There is a need for high performance algorithms to map these sequences to the refer...
Sanchit Misra, Ramanathan Narayanan, Wei-keng Liao...
IC
2004
13 years 9 months ago
Constructing Finite State Automata for High-Performance XML Web Services
This paper describes a validating XML parsing method based on deterministic finite state automata (DFA). XML parsing and validation is performed by a schema-specific XML parser th...
Robert van Engelen