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FPL
2006
Springer
105views Hardware» more  FPL 2006»
13 years 11 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
JVM
2004
103views Education» more  JVM 2004»
13 years 9 months ago
The Virtual Processor: Fast, Architecture-Neutral Dynamic Code Generation
Tools supporting dynamic code generation tend too be low-level (leaving much work to the client application) or too intimately related with the language/system in which they are u...
Ian Piumarta
ICSM
1999
IEEE
14 years 7 days ago
Recovering High-Level Views of Object-Oriented Applications from Static and Dynamic Information
Recovering architectural documentation from code is crucial to maintaining and reengineering software systems. Reverse engineering and program understanding approaches are often l...
Tamar Richner, Stéphane Ducasse
FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
13 years 11 months ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...
SAIG
2000
Springer
13 years 11 months ago
Generating Data Analysis Programs from Statistical Models
Extracting information from data, often also called data analysis, is an important scienti c task. Statistical approaches, which use methods from probability theory and numerical a...
Bernd Fischer 0002, Johann Schumann, Thomas Pressb...