Sciweavers

2 search results - page 1 / 1
» Generating physical addresses directly for saving instructio...
Sort
View
33
Voted
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 10 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
IPPS
2006
IEEE
14 years 5 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González