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» Generation of BDDs from hardware algorithm descriptions
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MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
14 years 14 hour ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
FASE
2006
Springer
13 years 11 months ago
Regular Inference for State Machines with Parameters
Techniques for inferring a regular language, in the form of a finite automaton, from a sufficiently large sample of accepted and nonaccepted input words, have been employed to cons...
Therese Berg, Bengt Jonsson, Harald Raffelt
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
14 years 2 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
WOSP
1998
ACM
14 years 1 days ago
Poems: end-to-end performance design of large parallel adaptive computational systems
The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runti...
Ewa Deelman, Aditya Dube, Adolfy Hoisie, Yong Luo,...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
14 years 2 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...