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» Generation of BDDs from hardware algorithm descriptions
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DFT
2006
IEEE
82views VLSI» more  DFT 2006»
14 years 1 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
IUI
2006
ACM
14 years 1 months ago
Interactive learning of structural shape descriptions from automatically generated near-miss examples
Sketch interfaces provide more natural interaction than the traditional mouse and palette tool, but can be time consuming to build if they have to be built anew for each new domai...
Tracy Hammond, Randall Davis
FMSD
2007
110views more  FMSD 2007»
13 years 7 months ago
Exploiting interleaving semantics in symbolic state-space generation
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...
Gianfranco Ciardo, Gerald Lüttgen, Andrew S. ...
ACL
1997
13 years 9 months ago
An Algorithm for Generating Referential Descriptions with Flexible Interfaces
Most algorithms dedicated to the generation of referential descriptions widely suffer from a fundamental problem: they make too strong assumptions about adjacent processing compon...
Helmut Horacek
ERSA
2009
149views Hardware» more  ERSA 2009»
13 years 5 months ago
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
Hassan Edrees, Brian Cheung, McCullen Sandora, Dav...