VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. We will present the underlying algorithm, point out the difficulties for the hardware implementation and will provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method we also present some measurement results from a prototype implementation.

• Type: Conference
• Year: 2006
• Where: DFT
• Authors: Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf
• Keywords: Clock Generation Method, DFT 2006, Fault-tolerant Clock Generation, Hardware, Hardware Implementation