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» Generation of design guarantees for interconnect matching
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INFOCOM
2003
IEEE
14 years 24 days ago
On Guaranteed Smooth Scheduling For Input-Queued Switches
— Input-queued switches are used extensively in the design of high-speed routers. As switch speeds and sizes increase, the design of the switch scheduler becomes a primary challe...
Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman...
DAC
2005
ACM
13 years 9 months ago
Piece-wise approximations of RLCK circuit responses using moment matching
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
INFOCOM
2003
IEEE
14 years 24 days ago
Local Scheduling Policies in Networks of Packet Switches with Input Queues
— A significant research effort has been devoted in recent years to the design of simple and efficient scheduling policies for Input Queued (IQ) and Combined Input Output Queue...
Marco Ajmone Marsan, Paolo Giaccone, Emilio Leonar...
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 1 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
ISQED
2000
IEEE
136views Hardware» more  ISQED 2000»
13 years 12 months ago
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
Mohamed Dessouky, Marie-Minerve Louërat