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DAC
2007
ACM
14 years 9 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
PLDI
2009
ACM
14 years 3 months ago
Snugglebug: a powerful approach to weakest preconditions
Symbolic analysis shows promise as a foundation for bug-finding, specification inference, verification, and test generation. This paper addresses demand-driven symbolic analysi...
Satish Chandra, Stephen J. Fink, Manu Sridharan
ISSTA
2006
ACM
14 years 2 months ago
Application of automated environment generation to commercial software
Model checking can be an effective technique for detecting concurrency-related errors in software systems. However, due to scalability issues, to handle industrial-strength softw...
Oksana Tkachuk, Sreeranga P. Rajan
DAC
2007
ACM
14 years 9 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
DAC
2003
ACM
14 years 9 months ago
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...