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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 1 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
HPDC
2006
IEEE
14 years 1 months ago
Materializing Highly Available Grids
Grids are becoming a mission-critical component in research and industry. The services they provide are thus required to be highly available, contributing to the vision of the Gri...
Mark Silberstein, Gabriel Kliot, Artyom Sharov, As...
HPDC
2005
IEEE
14 years 1 months ago
Recording and using provenance in a protein compressibility experiment
Very large scale computations are now becoming routinely used as a methodology to undertake scientific research. In this context, ‘provenance systems’ are regarded as the equ...
Paul T. Groth, Simon Miles, Weijian Fang, Sylvia C...
PLDI
1997
ACM
13 years 12 months ago
Flick: A Flexible, Optimizing IDL Compiler
An interface definition language (IDL) is a nontraditional language for describing interfaces between software components. IDL compilers generate “stubs” that provide separat...
Eric Eide, Kevin Frei, Bryan Ford, Jay Lepreau, Ga...
IWAN
2000
Springer
13 years 11 months ago
A Flexible IP Active Networks Architecture
This paper presents the main concepts of the IST Project FAIN "Future Active IP Networks" [10], a three-year collaborative research project, whose main task is to develo...
Alex Galis, Bernhard Plattner, Jonathan M. Smith, ...