Sciweavers

494 search results - page 89 / 99
» Generic Design Space Exploration for Reconfigurable Architec...
Sort
View
ISPASS
2007
IEEE
14 years 1 months ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...
SC
2009
ACM
14 years 2 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally
DAC
1995
ACM
13 years 11 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
14 years 4 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
SC
2009
ACM
14 years 2 months ago
Robust workflows for science and engineering
Scientific workflow tools allow users to specify complex computational experiments and provide a good framework for robust science and engineering. Workflows consist of pipelines ...
David Abramson, Blair Bethwaite, Colin Enticott, S...