Sciweavers

305 search results - page 8 / 61
» Geometric programming for circuit optimization
Sort
View
GECCO
2000
Springer
150views Optimization» more  GECCO 2000»
14 years 2 months ago
Automatic Synthesis of Electrical Circuits Containing a Free Variable Using Genetic Programming
A mathematical formula containing one or more free variables is "general" in the sense that it represents the solution to all instances of a problem (instead of just the...
John R. Koza, Martin A. Keane, Jessen Yu, William ...
ICCD
2006
IEEE
86views Hardware» more  ICCD 2006»
14 years 7 months ago
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
Rasit Onur Topaloglu, Andrew B. Kahng
DAC
2005
ACM
14 years 25 days ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
FOCS
1992
IEEE
14 years 3 months ago
Dynamic Half-Space Reporting, Geometric Optimization, and Minimum Spanning Trees
We describe dynamic data structures for half-space range reporting and for maintaining the minima of a decomposable function. Using these data structures, we obtain efficient dyna...
Pankaj K. Agarwal, David Eppstein, Jirí Mat...
EUROGP
2008
Springer
128views Optimization» more  EUROGP 2008»
14 years 19 days ago
Hardware Accelerators for Cartesian Genetic Programming
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidat...
Zdenek Vasícek, Lukás Sekanina